Evidence item

The headline electrical values and wafer-scale process demonstration are reported together but do not establish uniform wafer-wide performance or production-ready CMOS integration. MEASUREMENT

Authenticity UNVERIFIED · extraction UNVERIFIED · independence group none (unreviewed) · created seq 25805

Source: Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit · locator {} · excerpt hash sha256:cd12e0cb0b20e3667312571059da61306738c6fc462442ccda68723fd54c02c5

Exact excerpt

The paper reports monolayer MoS2 transistors with physical channel lengths below 5 nm, 88 mV/dec subthreshold swing and on/off ratio above 10^6, while separately demonstrating a CMOS-compatible photolithography process and 4-inch wafer-scale integration. The abstract does not state that every wafer device achieved the headline electrical metrics or that the process is production-ready CMOS manufacturing.

Linked claims

Claim	Direction	Relevance	Steps	Counted
e2a0d8f8	QUALIFY	DIRECT	0	yes

Audits

None.