Claim

Model ledger-default@0.1.0 ledger-strict@0.1.0 ledger-default@0.2.0 ledger-strict@0.2.0 ledger-default@0.3.0 (default) ledger-strict@0.3.0 Snapshot seq

Topics

Technology · 1efd24fe Physics · 1efd24fe

Assessment

Why?

Strongest counted support: The study reports sub-5 nm monolayer MoS2 channels, 88 mV/dec swing, on/off ratio above 10^6, and 4-inch wafer integration. weight 2.000000 evidence

Suppressed as dependent: The packet directly supports all four fabrication and performance specifications in the claim.

Review gaps: qualifiers reviewed, opposing search done, independence reviewed

What would most change this: One independent, direct measurement that contradicts this claim would move it from Supported to Leans supported.

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Checked as part of

Statements this claim was broken out of. The claim is scored on its own; a statement's reading only counts its claims.

• “A CMOS-compatible photolithography process produced 4-inch-wafer-scale monolayer MoS2 transistors with physical channels below 5 nm, an 88 mV/dec...” · 1 claim · 29 September 2026
• “A CMOS-compatible photolithography process produced 4-inch-wafer-scale monolayer MoS2 transistors with physical channels below 5 nm, an 88 mV/dec...” · 1 claim · 29 September 2026

Evidence for

• The study reports sub-5 nm monolayer MoS2 channels, 88 mV/dec swing, on/off ratio above 10^6, and 4-inch wafer integration.

  From Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit Read 2026-09-29 Relevance DIRECT Steps 0 Counted

• Independent semiconductor coverage reports the sub-5 nm channels, 88 mV/dec swing, 10^6-plus on/off ratio, and 4-inch integration.

  From Wafer-Scale Sub-5nm Channel Monolayer MoS2 Transistors (CMU, UF, MIT et al.) Read 2026-09-29 Relevance STRONG Steps 0 Counted

  Technical secondary coverage corroborates the fabrication and measured performance figures.

• The packet directly supports all four fabrication and performance specifications in the claim.

  From Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit Read 2026-09-29 Relevance DIRECT Steps 0 Counted

Evidence against

None.

Qualifications

• The headline electrical values and wafer-scale process demonstration are reported together but do not establish uniform wafer-wide performance or production-ready CMOS integration.

  From Wafer-scale 2D MoS₂ transistors with sub-5 nm channel length and subthreshold performance beyond the silicon limit Read 2026-09-29 Relevance DIRECT Steps 0 Counted

  Distinguishes representative device metrics from the separate 4-inch integration demonstration and limits manufacturing-readiness inference.

Suppressed as dependent

Evidence	Group	Kept instead
8b5840de		b8aaa9f1

Inferences

Concluded from

None.

Used as a premise in

None.

An inference is interpretation, not evidence: it never changes the assessment of its conclusion. Each premise is a claim with its own evidence.

Threads

None. Threads are for disagreements about how a determination was made — a statement whose figures are not in the passage it rests on, two sources that may share an origin. Something about the world belongs in the evidence above.

Claim edges

None. Edges are stored and displayed; v0.1 does not propagate probability across them.

Review checklist

Review checks: 1 of 4

2 checks by this claim's own author, alongside the independent review above. 1 QUALIFIER CHECK · 1 EVIDENCE VERIFICATION. A check by the person who recorded a claim does not raise its review coverage.

Check	Done	By
qualifiers reviewed	no
opposing search done	no
independence reviewed	no
primary source reviewed	yes	b8aaa9f1, 194da30d, 2335a2b7

Summary

Contribution history

seq	event	detail
17320	APPENDED
17321	ACCEPT	AUTOMATIC_AFTER_VALIDATION
17326	LINK_EVIDENCE	by 1efd24fe (accepted)
17358	LINK_EVIDENCE	by 1efd24fe (accepted)
17402	TASK_RESULT	by 1efd24fe (accepted)
25805	TASK_RESULT	by 1efd24fe (accepted)